Model order reduction method for interconnect modeling in IC design

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035	⊔	⊔	‡a(OCoLC)47782548
100	1	⊔	‡aWang, Meiling.
245	1	0	‡aModel order reduction method for interconnect modeling in IC design / ‡cby Mei-ling Wang.
260	⊔	⊔	‡c2000.
300	⊔	⊔	‡axi, 168 leaves : ‡bill. ; ‡c28 cm.
502	⊔	⊔	‡aThesis (Ph.D. in Engineering-Electrical Engineering and Computer Sciences)--University of California, Berkeley, Fall 2000.
504	⊔	⊔	‡aIncludes bibliographical references (leaves 148-149).
538	⊔	⊔	‡aMode of access: Internet.
610	2	0	‡aUniversity of California, Berkeley. ‡bDept. of Electrical Engineering and Computer Sciences ‡xDissertations.
690	⊔	⊔	‡aDissertations, Academic ‡xUCB ‡xEngineering ‡y1991-2000.
CID	⊔	⊔	‡a100847633
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DAT	1	⊔	‡a20151201090528.0 ‡b2024-03-30T18:04:49Z
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