A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits /
Daniel L. Palumbo and George B. Finelli.

Description

Main Author

Palumbo, Daniel L.

Related Names

Finelli, George B.
Langley Research Center.

Language(s)

English

Published

Washington, D.C. : National Aeronautics and Space Administration, Scientific and Technical Information Office ; 1987.

Subjects

Electronic digital computers.
Fault-tolerant computing.
Integrated circuits > Integrated circuits / Very large scale integration > Integrated circuits / Very large scale integration / Computer simulation > Integrated circuits / Very large scale integration / Computer simulation / Evaluation.

Note

Prepared at Langley Research Center.
"September 1987"--Cover.

Physical Description

iii, 41 p. : ill. ; 28 cm.

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