Hierarchical clock routing scheme for multi-chip modules based on area pad interconnection

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035	⊔	⊔	‡asdr-ucsc.b18882651
040	⊔	⊔	‡aCUZ ‡cCUZ
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090	⊔	⊔	‡aQA75.5 ‡b.T43 1993:45
035	⊔	⊔	‡a(OCoLC)34535162
100	1	⊔	‡aZhu, Jing
245	1	0	‡aHierarchical clock routing scheme for multi-chip modules based on area pad interconnection / ‡cQing Zhu, Wayne W.M. Dai
260	⊔	⊔	‡aSanta Cruz, CA : ‡bComputer Research Laboratory, University of California, Santa Cruz, ‡c[1993]
300	⊔	⊔	‡a16 p. : ‡bill. ; ‡c28 cm
490	0	⊔	‡aTechnical report / Computer Research Laboratory, UCSC ; ‡vUCSC- CRL-93-45
538	⊔	⊔	‡aMode of access: Internet.
650	⊔	0	‡aSteiner systems
650	⊔	0	‡aElectronic data processing ‡xDistributed processing
650	⊔	0	‡aReal-time clocks (Computers)
650	⊔	0	‡aMultichip modules (Microelectronics)
700	1	⊔	‡aDai, Wayne Wei-Ming
710	2	⊔	‡aUniversity of California, Santa Cruz. ‡bComputer Research Laboratory
CID	⊔	⊔	‡a008316763
DAT	0	⊔	‡a19960409014108.0 ‡b20111212000000.0
DAT	1	⊔	‡a20120815095258.0 ‡b2024-05-04T17:55:05Z
CAT	⊔	⊔	‡aSDR-UCSC ‡dIII - MILLENIUM ‡lloader.pl-001-001
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